1. Field of the Present Invention
The present invention relates to the field of data processing systems, and more particularly, to address translation mechanisms such as translation lookaside buffer (TLBs) and facilities for responding to an error detected during the address translation process.
2. History of Related Art
Data processing systems employing virtual addressing schemes are well known in the field of microprocessor based data processing systems. In a virtual address machine, each program can access the complete effective address (EA) of the system. To accommodate multiple programs running simultaneously, a virtual address (VA) is utilized. The virtual address space is larger than the effective address space so that operating system can allocate separate regions of the virtual address space to each program. Typically, the operating system associates some portions of the effective address space with private virtual address space regions for exclusive use by a program when the program is started. These private regions are not accessible to a second program. Other regions of the effective address space are associated with shared virtual address space regions that are accessible to some or all other programs. These shared regions may contain, for example, operating and subroutine libraries.
When an instruction that references an address in memory such as a load or store instruction is executed, the effective address of the instruction must be translated before the memory can be accessed. The address translation process may include translating the effective address to an intermediate address known as the virtual address and then converting the virtual address to a real address or physical address. The translation from an effective address to a virtual address is typically performed using a segment-lookaside-buffer (SLB) or a segment register, the content of which replaces some of the high order bits of the effective address. The resulting virtual address is subsequently translated to a real address using a translation-lookaside-buffer (TLB) or a page table. The TLB is a cache of the content of page table entries that have been used recently to translate virtual address.
The two step address translation described can reduce the performance of the processor. To address the performance penalties associated with a two step address translation, the processor may implement one or more effective-to-real address tables (ERATs) to translate effective addresses directly to real addresses. These ERATs are cache tables that contain the results of recent address translations. When an address generated by a program misses in the ERAT, the address translation must be performed using the SLB. If the program address also misses in the TLB, the TLB must be reloaded from system memory. The program latency associated with a memory access resulting from a TLB miss is significant enough to warrant the use of relatively large TLBs to reduce the TLB miss rate to an acceptable level.
For systems using 64 bits or more of addressing, the increasingly large number of entries desirable for an adequate TLB results in a TLB unit that occupies a significant area of the processor. As the size of the TLB grows, the likelihood that the TLB contains an error increases. It would therefore be desirable to implement a mechanism by which errors in the TLB would be quickly identified. It would be further desirable if the implemented solution were able to respond to a TLB with a precise exception routine.